A. Field of the Invention
This invention relates to programmable digital data processors, with emphasis on the improvement of the performance on buffering storage systems associated with such data processors. More particularly, it relates to a means of addressing these storage devices, also called herein CACHE memories, in a more rapid manner.
B. Prior Art
Many increases in computing rates have been achieved through advances in physical technologies relating to hardware and hardware functioning. The advent of integrated circuitry gave rise to circuit components operable at extremely high computing rates. They are capable of performing complex functions while remaining economically feasible. Access to, and cycle times of, storage systems have also been markedly increased.
In addition to the changes and developments in the hardware, there have been continuing advances in the organizational architecture of such digital data processing systems that provide for ever increasing utilization of the various data processing components.
While many examples of optimization of the utilization of the various components comprising the digital data processing system can be described, attention will be directed herein to the concept of increasing data processing throughput rates by providing a system which improves the performance of an instruction buffer device by increasing the speed at which it is accessed to correspondingly increase its informational output rate.
It has been known for some time that a Content Addressable Memory (CAM) may be used to make references to an instruction buffer. The present instruction buffer contains a total of sixteen (16) pages of 256 words each. Each page is individually addressable. It is also well known that a content addressable memory is addressably accessed and provides a corresponding address output (provided it resides therein) in a single clock time.
There is an extensive description of the use of a content addressable memory as an addressing means for a CACHE memory set forth in U.S. Pat. No. 3,848,234, entitled "Multi-Processor System with Multiple CACHE Memories" by Thomas Richard MacDonald and assigned to the same assignee as the present invention. The contents of that application are intended to be incorporated into this application by this reference.
It is seen from a reading of that patent that is also has been known for some time that an instruction buffer system may be used for providing sequential instructions to control processor operations. Although there may be many different instructions, a suggested format of a preferred instruction is disclosed herein. Basically, the present format is usually shown as a 36-bit word having a function portion, a definition portion, an address selection portion and an address offset portion.
More specifically, an address is presented to a content addressable memory (also known as an associative memory) and if the presented address matches any one of the addresses contained in the memory, that location is actuated and a proper CACHE address is generated. Since it takes one clock cycle to accomplish the content addressable memory operation and a further clock cycle to operate the instruction buffer, the overall operation consumes two clock cycles. Thus, this usual method of referencing the instruction buffer allows the CACHE memory to be referenced every two clock cycles. In the prior configuration this was accomplished in sixty nanoseconds, since a single clock cycle was thirty nanoseconds.